Broadband wireless communication devices such as a tuner used in television broadcasts via cable transmission or wireless transmission require a variable gain amplifier with high linearity (small distortion) to suppress intermodulation interference between different channels in response to input of a strong signal. Conventional tuners made up of discrete parts have adopted an attenuator with highly linear PIN diode components to prevent entry of a strong signal into the amplifier and thus suppress an intermodulation interference signal. However, the PIN diodes cannot be formed on a common semiconductor integrated circuit such as a CMOS or bipolar semiconductor integrated circuit. Thus, in order to realize a wireless communication device on a semiconductor integrated circuit, a different type of variable gain amplifier is needed.
An example of such a variable gain amplifier is disclosed in U.S. Pat. No. 6,100,761 (Highly Linear Variable-Gain Low Noise Amplifier; issued Aug. 8, 2000). This amplifier, as shown in FIG. 23, is provided with an NPN transconductance pair which includes transistors IQ1 and IQ2. To the collector of the transistors IQ1 and IQ2 is applied a power voltage Vc via a variable resistor 1Rc, and the emitter is connected to a GND line via a variable resistor 1Re. The transistors IQ1 and IQ2 have IN+ and IN− at their bases, respectively, and receive a bias voltage vb via resistors 1Rb1 and 1Rb2, respectively.
The gain of the amplifier is given by 1Rc/(1/gm+1Re), where gm is the transconductance of the transistors IQ1 and IQ2. This amplifier realizes variable gain control by the circuit structure, as shown in FIG. 24, in which the variable resistor 1Re is configured with a resistor ladder of resistors Rn1, Rn2, Rn3, . . . , and so on, and nMOS switches Mn1, Mn2, Mn3, . . . , and so on, which are connected between the resistors. The nMOS switches Mn1, Mn2, Mn3, . . . , and so on are switched open or closed by the respective voltages Vn1, Vn2, Vn3, and so on received at the gates.
However, the foregoing amplifier has the following three problems.
Firstly, accurate designing of the resistor ladder requires a low ON resistance for the nMOS transistors switches Mn1, Mn2, Mn3, . . . , and so on. However, in order to fabricate a switch with an ON resistance of 1 Ω using, for example, a standard CMOS process of 0.25 μm, a gigantic transistor with a channel width of 1000 μm will be required. The resistor ladder requires a plurality of such gigantic transistors. The result of this is an increased mount area.
Secondly, a change in resistance value of the variable resistor 1Re varies the value of the current in the circuit, which causes the operating point of the transistors to fluctuate. This fluctuation of the operating point is suppressed by the provision of an adjuster circuit of a bias voltage Vb, as shown in FIG. 25. In the adjuster circuit shown in FIG. 25, a resistor 5Rb is connected between the collector and base of a transistor 5Q1, and a variable resistor 5Re is provided between the emitter of the transistor 5Q1 and a GND line. Further, a bias current 51c is flown into the junction of the resistance 5Rb and the collector, and a voltage 5Vb at the collector is outputted as a bias voltage Vb via a buffer amplifier 501. However, because this adjuster circuit includes the resistor 5Rb, which is a replica of the resistor ladder, the mount area is again increased.
Thirdly, disregarding the bipolar transistors used in FIG. 23 and FIG. 25, the following considers a circuit which incorporates a MOS transistor, instead of the bipolar transistor, which can be provided by the CMOS process, which is less expensive than the BiCMOS process. Current I through the MOS transistor is given byI=K·(W/L)·Vod2  (1).
Here, K is a process-dependent constant, W is the channel width of the transistor, and L is the channel length of the transistor. Further, Vod=Vgs−Vth, and Vgs=Vg−Vs, where Vg is the gate voltage, Vs the source voltage, and Vth the threshold voltage of the transistor. According to this arrangement, voltage Vod does not change even when the resistance value of the variable resistor 1Re is varied to reduce gain, because the adjuster circuit of a bias voltage Vb operates to flow a constant current.
Incidentally, RF Linearity of Short-Channel MOSFETs, Theerachet Soorapanth and Thomas H. Lee, First International Workshop on Design of Mixed-Mode Integrated Circuits and Applications, Cancun, Mexico, Jul. 28–30, 1997, pp. 81–84 teaches the concept of IIP3 (third-order Input Intercept Point), which is an index of third-order distortion component of the circuit, and is an input value at which the third-order intermodulation component in response to a two-tone input takes the value of the first-order component. FIG. 5 of this publication indicates that the IIP3 of the MOS transistor is determined by the value of Vod. Therefore, the IIP3 will not change even when the gain of the amplifier is changed by varying the resistance value of the variable resistor 1Re.